1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly relates to a semiconductor integrated circuit having a clock signal generation circuit.
2. Description of the Related Art
In recent years, semiconductor integrated circuits each including a memory 200 and a memory controller 100 like a semiconductor integrated circuit of a first conventional technique shown in FIG. 12 have been increasing. The memory controller 100 is provided for controlling the memory 200. In synchronization with a clock signal CLK, the memory controller 100 outputs an address ADDR, write data WD and memory control signals when writing data to the memory 200, and outputs the address ADDR and the memory control signals when reading data from the memory 200. Note that the memory control signals consist of: a chip select signal CS to activate a specific memory, a read/write signal nRW to differentiate between write and read operations (a signal indicating a read operation at a low level, and a write operation at a high level) and a byte write signal EN. Hereinafter, brief description will be given of the operations based on the first conventional technique.
As shown in FIG. 13, when writing data to the memory 200, the memory controller 100 performs the following operation. Specifically, at a time T1, the memory controller 100 outputs the address ADDR and the write data WD, and asserts the chip select signal CS and the read/write signal nRW, which are the memory control signals. Then, at a time T2 when a clock cycle after from the time T1, the memory controller 100 deasserts the memory control signals CS and nRW. Note that it is assumed that the condition that both the memory control signals CS and nRW are asserted indicates a write operation, and the condition that only the chip select signal CS is asserted indicates a read operation. Meanwhile, at the time T1 according to the clock signal CLK, the memory 200 receives the address ADDR, the write data WD and the asserted memory control signals CS and nRW, and then performs a write operation by writing the write data WD to a memory area specified by the address ADDR. Note that, in FIG. 12, the memory control signals are supplied to the memory 200 via an Inverter 300 so as to be received by the memory 200 as low active signals.
On the other hand, when reading data from the memory 200, the memory controller 100 performs the following operation. Specifically, at a time T1, the memory controller 100 outputs the address ADDR and asserts only the chip select signal CS of the memory control signals. Then, at the time T2, the memory controller 100 deasserts the chip select signal CS. At a time Tlat−1 after a lapse of a predetermined latency time from T1, the memory 200 outputs read data specified by the address ADDR in response to the chip select signal CS received at the time T1. The memory controller 100 receives the read data RD outputted at the time Tlat−1.
With the first conventional technique as described above, as can be seen from FIG. 13, the memory controller 100 outputs the chip select signal CS, the read/write signal nRW, the address ADDR, and the write data WD at the time T1, in writing. Therefore, the memory 200, which simultaneously receives these signals, can no longer secure a setup time of the address and the write data before receiving the chip select signal CS and the read/write signal nRW. As a result, a setup violation occurs.
A second conventional technique as shown in FIG. 14 is used in order to solve the setup violation. In other words, in the second conventional technique, when writing data to the memory 200, a flip flop 400 is placed for each of the chip select signal CS and the read/write signal nRW which are outputted from the controller 100 at the time T1, so that the chip select signal CS and the read/write signal nRW are supplied to the address ADDR after being delayed for two clock cycles as shown in FIG. 15. This enables the memory 200 to secure a setup time between: the address ADDR and the write data WD; and the chip select signal CS and the read/write signal nRW.
Related techniques to a memory controller for controlling a memory, as described above, is disclosed in L220 Cache Controller Revision rlp 7 Technical Reference Manual ARM (http://infocenter.arm.com/help/topic/com.arm.doc.ddi0329i/DDI0329.pdf).
The inventor of the present invention found out the following problem with the second conventional technique as described above. As an increasingly faster clock signal CLK is supplied to the memory, a setup time between the clock signal CLK and the control signals, consisting of the chip select signal CS, the read/write signal nRW and the byte write signal EN, cannot be secured in the second conventional technique shown in FIG. 14 either.